This Makefile in this directory is used to create tab files from the verilog simulation of the Edge Walker module. The Makefile in the ./qsim directory can be used to run Qsim using the generated tab files. No comparison of C and Verilog simulations is attempted.
| Name |
Last commit
|
History
|
Last Update |
|---|---|---|
| .. | ||
| CVS | ||
| InData | ||
| OutData | ||
| Wir.DELETED | ||
| qsim | ||
| Makefile | ||
| README | ||
| testit |