To generate:
nrandring --- generate nrandring vector
vsram --- generate virage sram test vector
Please note: (1) vcs 6.2 result is different from 6.0.1.
(2) JTAG_CLK is 5MHz
dc.cpu --- use sim.cpu.ipc to get vector
dc --- use sim.ipc to get vector
Please be aware:
(1) The dump file of two runs will have some difference at time 0.
(2) If in hw/chip/src/bb.v
assign pll_lock[1] = pllx2_lock | pll_bypass;
assign pll_lock[0] = pllc_lock | pll_bypass;
may be changed to
assign pll_lock[1] = pll_bypass;
assign pll_lock[0] = pll_bypass;
to make NEC happy.