- IOSIM INFORMATION - (Updated: 11/10/94) This file contains information on how to set up and use the IOSIM environment. There are two main components for this environment function: the verilog process and the C iosim process. Streams sockets are used to communicate between these 2 processes. The inter-process communication (IPC) is implemented as PLI library for the verilog process. Acting as the server, the verilog process receives requests from iosim, processes the requests, and returns the result to its client. Most of the requests are memory reads and writes. In iosim test environment, all accesses to the RCP memory address space are converted to the R4000 K1 segment space. This automatically generates an exception by UNIX since K1 segment is in kernel space. Thus, in the iosim exception handler, the RCP physical address is extracted out from the exception address and based on either a store/load instruction, the proper write/read request is sent to the verilog process. The verilog process (via the r4200b.v module) receives the request, generates the proper signals on the MBUS to either read/write from/to a memory address (i.e., RDRAM, SP registers), collects the data, and sends it back to iosim. During all this time, iosim is blocked in the exception handler, waiting for the response from verilog. Upon receiving valid data, iosim exception handler inserts the data into the proper CPU registers, increments the exception PC, and returns from exception. The iosim application can now continue to process the next test. First, you need to build the 'C' iosim environment: 1. p_tupdate $ROOT/PR/iosim - This will get pli, src, and test directories. The pli directory contains the IPC library for verilog to use. The src directory contains all the source and binaries for the 'C' iosim environment. 2. make - This will build the pli and src directories Second, you need to build the 'Verilog' iosim environment: 1. Make sure that you all the appropriate RCP verilog files. p_tupdate $ROOT/PR/hw/chip/rcp p_tupdate $ROOT/PR/hw/chip/lib 2. p_tupdate $ROOT/PR/hw/chip/sim - This will extract all the template top-level verilog files (such as reality.v, cg.v, r4200b.v, and others) needed to build the RCP chip. 3. make ipc - This will build the verilog executable and put all the output files (including *.o and *.c in csrc, simv.ipc, and simv.ipc.daidir) in $SIMVDIR directory. The default setting for SIMVDIR=/var/tmp/$USER. - You can override the SIMVDIR variable by setting it in the make command line (i.e. make SIMVDIR=/tmp ipc) - You should browse the Makefile for more information. Now, you're ready to run some tests: 1. You can start the 'C' iosim first by typing: $ cd $ROOT/PR/iosim/src $ ./iosim -d 0x41 -f ../test/si.tst -l io.log where -d <debug_flag in hex> (default is 0) -f <test_file> (default is 'io.tst') -l <log_file> (default is stderr) -h (print usage message) This will start the 'C' process and it will try forever to make connection with the verilog server. The test file in this example is used to test the Serial Interface (SI). 2. You can now start the 'Verilog' process by typing: $ cd $SIMVDIR $ ./simv.ipc +load_pif +mbus_mon +mmap_rdram=filename where +load_pif - pre-loaded the PIF with test data (read from file 'pif.data') +mbus_mon - turn on MBUS monitoring +mmap_rdram - preloads rdram. The file will also contain the result rdram data after simulation is finished. Other useful options are: +load_rom - pre-loaded the ROM with test data (read from rom_4.data and rom_8.data) +dump - generate the verilog dump 3. Once 'simv.ipc' is up and ready, 'iosim' will make the connection and send over requests to access memory.